1. Field of the Invention
This invention relates to integrated circuits employing copper interconnects and more particularly to the control of the copper interconnect microstructure to obtain improved interconnects.
2. Description of the Related Art
A major limiting factor in ULSI interconnect technology is RC time delay introduced by the coupling of metal-insulator characteristics. An efficient interconnection scheme for advanced ULSI circuits requires materials with low effective time constants. In this regard, metals with low resistivity such as copper and the noble metals are emerging as materials of choice.
Some of the issues to be addressed in order for Cu-based interconnects to be a viable choice, especially as integration density continues to rise, involves the processes for patterning the copper lines, the prevention of diffusion of the copper into the underlying active substrate, the prevention of air corrosion on the surface of the copper and the uniformity of the microstructure of the copper. The issue of controlling and obtaining uniformity of the microstructure of the electroplated copper is addressed herein.
A more detailed background of the art regarding copper interconnects can be found with reference to the following publications which are incorporated herein by reference: R. L. Jackson, et al., xe2x80x9cProcessing and integration of copper interconnectsxe2x80x9d, Solid State Technology, 49-59, March 1998; X. W. Lin et al., xe2x80x9cFuture interconnect technologies and copper metallizationxe2x80x9d, Solid State Technology, 63-79, October 1998; and P. Singer, xe2x80x9cTantalum, Copper and Damascene: The Future of Interconnectsxe2x80x9d, Semiconductor International, 91-98, June 1998.
Also, one may refer to The Metals Handbook, 8th Edition, Vol. 1, page 802, xe2x80x9cProperties and Selection of Metalsxe2x80x9d, wherein various alloys of copper are discussed with respect to their physical and electrical properties and uses, including uses in connectors and sliding contacts, and which is incorporated herein by reference. It may be noted that there is no mention of the use of such alloys in IC""s, nor of the self annealing problem of copper interconnects in IC""s.
The recrystallization of electrodeposited copper due to self annealing and subsequent device processing which changes the mechanical and metallurgical properties of the copper requires a thorough understanding of microstructure control. If structural/property relationships and effects of annealing parameters are not well understood and controlled, a non-homogeneous microstructure can result which may lead to lower mechanical and electrical reliability of the finished integrated circuit device. Copper films have a tendency to self anneal over time. During this self annealing process, copper atoms migrate and cause the grain size of the microstructure to grow. This growth in grain size reduces sheet resistance and alters the mechanical properties of the film. Further, migration of copper atoms into underlying circuit elements e.g. the dielectric layers and/or the silicon are highly detrimental to device performance. It would therefore be desirable to control the copper microstructure to provide a uniform copper microstructure which is not substantially degraded by self annealing or during subsequent processing steps.
We now provide a method and structure to substantially eliminate the grain growth of copper due to self annealing. Basically, by properly alloying the copper interconnect, one can control and maintain the grain size of the copper and hence achieve a uniform microstructure while improving the strength, hardness and CMP removal rate of the interconnect while substantially maintaining the conductivity of the copper. Accordingly, the present invention is described as follows.
A method of making an integrated circuit having copper interconnects comprises alloying the copper of the interconnect with one or more elements which can control and maintain the grain size and grain boundaries of the copper, without significant loss of electrical properties, said alloying elements being present in an amount less than that which creates a second phase or precipitate within the alloy, at least at the annealing temperature.
The invention further includes the integrated circuit device having such alloyed copper interconnects.